HDLBits 系列（36）Arbitration circuit implemented by FSM

目录

原题复现

审题

我的设计

设计解释

---

 

原题复现

原题复现：

Consider the FSM described by the state diagram shown below:

This FSM acts as an arbiter circuit, which controls access to some type of resource by three requesting devices. Each device makes its request for the resource by setting a signal r[i] = 1, where r[i] is either r[1], r[2], or r[3]. Each r[i] is an input signal to the FSM, and represents one of the three devices. The FSM stays in state A as long as there are no requests. When one or more request occurs, then the FSM decides which device receives a grant to use the resource and changes to a state that sets that device’s g[i] signal to 1. Each g[i] is an output from the FSM. There is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device making a request when the FSM is in state A. Once a device, i, is given a grant by the FSM, that device continues to receive the grant as long as its request, r[i] = 1.

Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM outputs, g[i], using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.

审题

一看描述一大堆，我们提取出关键的一句话：

The FSM stays in state A as long as there are no requests.

我的设计

之后，看着状态转移图就可以实现设计：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    
    localparam A = 0, B = 1, C = 2, D = 3;
    reg [1:0] state, next_state;
    always@(*) begin
        next_state = A;
        case(state)
            A: begin
                if(r[1]) next_state = B;
                else if(r == 3'b000) next_state = A;
                else if(r[2:1] == 2'b10) next_state = C;
                else if(r == 3'b100) next_state = D;
            end
            B: begin
                if(r[1] == 0) next_state = A;
                else if(r[1]) next_state = B;        
            end
            C: begin
                if(r[2] == 1) next_state = C;
                else if(r[2] == 0) next_state = A;
            end
            D: begin
                if(r[3]) next_state = D;
                else if(~r[3]) next_state = A;
            end
        endcase
    end
    
    always@(posedge clk) begin
        if(~resetn) state <= A;
        else state <= next_state;
    end
    reg [3:1] g_mid;
    assign g = g_mid;
    
    always@(*) begin
        case(state)
            A: begin
				g_mid = 0;
            end
            B: begin
                g_mid = 3'b001;
            end
            C: begin
                g_mid = 3'b010;
            end
            D: begin
                g_mid = 3'b100;
            end
            default: begin
                g_mid = 0;
            end
        endcase
    end

endmodule

测试成功。

设计解释

r代表请求，从低位到高位，优先级依次递减，就是这个意思。

值得一提的是，那句关键描述：The FSM stays in state A as long as there are no requests.

没有请求时，状态机的状态保持在A状态，我们实现的方式就是通过在always块的第一条语句加上默认语句：

always@(*) begin
        next_state = A;
        case(state)
            A: begin
                if(r[1]) next_state = B;
                else if(r == 3'b000) next_state = A;
                else if(r[2:1] == 2'b10) next_state = C;
                else if(r == 3'b100) next_state = D;
            end
            B: begin
                if(r[1] == 0) next_state = A;
                else if(r[1]) next_state = B;        
            end
            C: begin
                if(r[2] == 1) next_state = C;
                else if(r[2] == 0) next_state = A;
            end
            D: begin
                if(r[3]) next_state = D;
                else if(~r[3]) next_state = A;
            end
        endcase
    end