Art of Writing TestBenches （of Verilog HDL） Part - I

		Introduction //简介
		Writing a testbench is as complex as writing the RTL code itself. These days ASICs are getting more and more complex and thus verifying these complex ASIC has become a challenge. Typically 60-70% of time needed for any ASIC is spent on verification/validation/testing. Even though the above facts are well known to most ASIC engineers, still engineers think that there is no glory in verification. 写一个测试基准程序和写一个RTL代码一样复杂。目前，ASIC变得越来越复杂，因此，验证这些复杂的ASIC也是一个非常复杂的挑战。通常，任何ASIC花费的时间中的60%-70%的时间用在了verification、validation、testing中。 尽管大多数据ASIC工程师都非常了解这个事实，但是工程师们在verification中没有荣誉可言。
		I have picked up some examples from the VLSI classes that I used to teach during 1999-2001, when I was in Chennai. Please feel free to give your feedback on how to improve the tutorial below. 当作者1999-2001在Chennai时，我从VLSI课程中挑出的一些例子。 请提交你的反馈来提高下面的教程。
		Before you Start
		For writing testbenches it is important to have the design specification of "design under test" or simply DUT.  在写测试基准程序时，认真阅读待测设计或者待测设备的设计说明书是非常重要的。 Specs need to be understood clearly and a test plan, which basically documents the test bench architecture and the test scenarios (test cases) in detail, needs to be made. 测试说明书（specification）应该了解的非常清楚，并且测试计划应该生成测试层次和测试情形的细节的文档。
		Example - Counter //计数器举例
		Let's assume that we have to verify a simple 4-bit up counter, which increments its count whenever enable is high, and resets to zero when reset is asserted high. Reset is synchronous to clock. 假如我们要验证一个4-bit的up计数器。该计数器在enable=1时能够增加其计数；当reset = 1时，将复位为0. reset与时钟同步。
		Code for Counter
		1 //----------------------------------------------------- 2 // Design Name : counter 3 // File Name : counter.v 4 // Function : 4 bit up counter 5 // Coder : Deepak 6 //----------------------------------------------------- 7 module counter (clk, reset, enable, count); 8 input clk, reset, enable; 9 output [3:0] count; 10 reg [3:0] count; 11 12 always @ (posedge clk) 13 if (reset == 1'b1) begin 14 count <= 0; 15 end else if ( enable == 1'b1) begin 16 count <= count + 1; 17 end 18 19 endmodule You could download file counter.v here
		Test Plan // 测试计划
		We will write a self-checking test bench, but we will do this in steps to help you understand the concept of writing automated test benches. Our testbench environment will look something like the figure below. 我将写一个自我测试的测试程序。但是我们将一步一步来写这个测试程序，以便帮组你能深刻的理解自动化测试基准的概念。 我们的测试基准环境像下面这个图标所示的。
		DUT is instantiated in the testbench, and the testbench will contain a clock generator, reset generator, enable logic generator and compare logic, which basically calculates the expected count value of counter and compares it with the output of counter. DUT(待测设备）在测试基准程序中被实例化。该测试基准程序中将包含一个clock产生器，reset logical产生器，enable logical产生器， 和一个用于比较期待计数值和计数器输出的比较器。
		Test Cases 测试用例
		Reset Test : We can start with reset de-asserted, followed by asserting reset for few clock ticks and deasserting the reset, See if counter sets its output to zero. reset test: reset = 0, reset =1 for few clock ticks  reset  = 0; 查看计数器的输出是不是为0. Enable Test : Assert/deassert enable after reset is applied.  enable 测试：  Random Assert/deassert of enable and reset.  //随机设置 reset 和enable的值。
		We can add some more test cases; but we are not here to test the counter, rather to learn how to write test benches. 我们可以添加更多其它的测试用例。但是我们这里不仅仅是测试计数器而是在学怎么写测试基准程序（testbenches）

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