使用元件例化的方式以一位全加器构建出四位全加器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity yiwei is
    Port ( a : in std_logic;
           b : in std_logic;
           cin : in std_logic;
       cout: out std_logic;
           s : out std_logic);
end yiwei;
architecture Behavioral of yiwei is
begin
 s <= a xor b xor cin;
 cout <= (a and b) or ((a or b) and cin);
end Behavioral;

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity siwei is
PORT (
    m,n : in std_logic_vector (3 downto 0);
    r : out std_logic_vector (3 downto 0);
    x :in std_logic ;
    y :out std_logic   
    );
end siwei;

architecture jiafaqi of siwei is

 component yiwei
   Port (  a : in std_logic;
           b : in std_logic;
           cin : in std_logic;
       cout: out std_logic;
           s : out std_logic);
   end component;   
        
 
        
     signal t : std_logic_vector (4 downto 0);
begin 
  t(0) <= x;

  g: for i in 0 to 3 generate      
    --u2: yiwei port map ( m(i), n(i), t(i),  t(i+1),r(i) );
  --u2: yiwei port map ( m(i)=>a, n(i)=>b, t(i)=>cin,  t(i+1)=>cout,r(i)=>s );ÕâÐÐÊÇ´íÎóµÄд·¨
  u2: yiwei port map ( a=>m(i), b=>n(i), cin=>t(i),  cout=>t(i+1),s=>r(i) );
  end generate;

 y <= t(4);
end jiafaqi;