基于Verilog HDL的模60BCD码计数器设计

基于Verilog HDL的模60BCD码计数器设计

最近学习了verilog HDL语言，自己写了一个模60的计数器，计数编码是BCD码，可置位复位，带进位输出，代码如下

module counter_60(clkin, rst_n, ld, data, out, c);
input clkin, rst_n, ld;
input [7:0] data;
output [7:0] out;
output c;
    reg c = 0;
    reg[3:0] ten, unit;
    assign out = {ten, unit};
    always@(posedge clkin or negedge rst_n or posedge ld)
    begin   
        if(!rst_n)
            {ten, unit} <= 0;
        else if(ld)
            {ten, unit} <= data;
        else
        begin
            if(ten == 5)
            begin
                if(unit == 8)
                begin
                    c = 1;
                    unit <= unit+1;
                end
                else if(unit == 9)
                begin
                    c = 0;
                    {ten, unit} <= 0;
                end
                else
                    unit <= unit+1;
            end
            else if(unit == 9)
            begin
                ten <= ten+1;
                unit <= 0;
            end
            else
                unit <= unit+1;
        end
    end
endmodule

test bench文件如下

`timescale 1 ps/ 1 ps
module digitalClock_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clkin;
reg [7:0] data;
reg ld;
reg rst_n;
// wires                                               
wire c;
wire [7:0]  out;

// assign statements (if any)                          
digitalClock i1 (
// port map - connection between master ports and signals/registers   
    .c(c),
    .clkin(clkin),
    .data(data),
    .ld(ld),
    .out(out),
    .rst_n(rst_n)
);

initial
begin
    rst_n = 1;
    ld = 0;
    clkin = 0;
    data = 0;
    #5 rst_n = 0;
    #5 rst_n = 1;
    repeat(2000)
        #5 clkin = ~clkin;
    data = {4'd4, 4'd7};
    ld = 1;
    #5 ld = 0;
    repeat(20)
        #5 clkin = ~clkin;
    $stop;
end                                     
endmodule