Circuits--Sequential Logic--Latches and Flip-Flops--Dualedge

网址：https://hdlbits.01xz.net/wiki/Dualedge
第一种解法：

module top_module (
    input clk,
    input d,
    output q
);
    reg  m = 1'b0;
    reg	 n = 1'b0;
    
    always@(posedge clk)
        begin
            m = d;
        end    
    
    always@(negedge clk)