Circuits--Sequential Logic--Finite State Machines--Fsm1

网址：https://hdlbits.01xz.net/wiki/Fsm1

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=1'b0;
    parameter B=1'b1; 
    reg state, next_state;

    always @(