Art of Writing TestBenches(of verilog HDL) Part - IV
AddingcompareLogic//添加比较逻辑Tomakeanytestbenchselfchecking/automated,firstweneedtodevelopamodelthatmimicstheDUTinfunctionality.为了是测试基准程序能偶自动校验,我首先要开发一个模型能够反应DuT的功能。Inourexample,it'sgoingtobeveryeasy,but