补码加减法器
一．实验原理
1. 补码的加法运算
补码的加法运算法则如下：[X+Y]补=[X]补+[Y]补
该式表明，两个有符号数相加的补码可以通过先分别对两个数求补码，然后相加得到。在采用补码形式表示时，进行加法运算时可以把符号位和数值位一起进行运算（若符号位有进位，则溢出不管），结果为两数之和的补码形式。
2.补码的减法运算
补码的减法运算法则如下：[X-Y]补=[X]补-[Y]补=[X]补+[-Y]补
该公式表明，求两个机器数的差值（如[X-Y]补）的补码，可以通过求被减数的补码（如[X]补）与减数的负值的补码（[-Y]补）的和得到。[-Y]补是对减数进行求负操作，求负的规则是全部位（含符号位）取反后再加1（实际上也是分别对符号位和真值位进行求反，因为正数与负数的符号也正好相反）。
3. 基本的加减法器结构如图所示，该加减法器可完成二进制补码的加、减法运算，用单符号位来判断运算是否溢出。
FA为一位全加器，M为运算控制，M=0做补码加法运算，M=1做补码减法运算，S0位运算结果的最低位，Sn-2为运算结果最高数值位，Sn为运算结果符号位，上图中采用单符号位法判断溢出，溢出条件为v=Cn⊕Cn-1
四．实验现象及结果分析
输入输出规则对应如下：
1.输入8位操作数A7-A0，对应开关SD15 -SD8
2. 输入8位操作数B7-B0，对应开关SD7 –SD0
3.最低位进位cin对应开关SA0
4.和sum7-sum0对应等A7-A0，最高位进位carryout对应灯A8
| 实现操作 |
操作数A |
操作数B |
结果 |
是否溢出 |
| M=0做补码加法运算 |
0000 0001 |
0000 0010 |
0000 0011 |
否 |
| 1111 1111 |
1000 0000 |
1 0111 1111 |
是 |
|
| M=1做补码减法运算 |
0000 0011 |
0000 0010 |
0000 0001 |
否 |
| 0111 1110 |
1111 1001 |
1 0111 1111 |
是 |
源代码1：
1. 全加器代码：
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYfull_adder IS
PORT
(
a,b,ci : IN STD_LOGIC;
s,co :OUT STD_LOGIC
);
ENDfull_adder;
ARCHITECTURErtl OF full_adder IS
BEGIN
s <= a xor b xor ci;
co <= (a and b) or (a and ci) or (b and ci);
END rtl;
2. 加减法器代码
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYadd8 IS
PORT
(
A,B :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
M : in std_logic;
S :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CO :OUT STD_LOGIC
);
END add8;
ARCHITECTURErtl OF add8 IS
COMPONENT full_adder IS
PORT
(
a,b,ci : IN STD_LOGIC;
s,co : OUT STD_LOGIC
);
END COMPONENT full_adder;
signal C0,C1,C2,C3,C4,C5,C6,C7 : STD_LOGIC;
signal C :STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
C(0)<=M xor B(0);
C(1)<=M xor B(1);
C(2)<=M xor B(2);
C(3)<=M xor B(3);
C(4)<=M xor B(4);
C(5)<=M xor B(6);
C(6)<=M xor B(6);
C(7)<=M xor B(7);
u0:full_adder PORT MAP(A(0),C(0),M,S(0),C0);
u1:full_adder PORT MAP(A(1),C(1),C0,S(1),C1);
u2:full_adder PORT MAP(A(2),C(2),C1,S(2),C2);
u3:full_adder PORT MAP(A(3),C(3),C2,S(3),C3);
u4:full_adder PORT MAP(A(4),C(4),C3,S(4),C4);
u5:full_adder PORT MAP(A(5),C(5),C4,S(5),C5);
u6:full_adder PORT MAP(A(6),C(6),C5,S(6),C6);
u7:full_adder PORT MAP(A(7),C(7),C6,S(7),C7);
CO<=C6 xor C7;
END rtl;
源代码2：
--1位的全加器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fulladder IS
PORT (
a, b : IN std_logic;
CarryIn : IN std_logic;
CarryOut: OUT std_logic;
Sum : OUT std_logic
);
END fulladder;
ARCHITECTURE fulladder_behav OF fulladder IS
BEGIN
CarryOut <= (a AND CarryIn) OR (b AND CarryIn) OR (a AND b);
Sum <= a XOR b XOR CarryIn;
END fulladder_behav;
--由全加器实现的8位行波进位加法器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder8 IS
PORT (
a : IN std_logic_vector(7 DOWNTO 0);
b : IN std_logic_vector(7 DOWNTO 0);
cin : IN std_logic;
cout : OUT std_logic;
sum : OUT std_logic_vector(7 DOWNTO 0)
);
END adder8;
ARCHITECTURE ripple OF adder8 IS
COMPONENT fulladder
PORT(
a, b, CarryIn : INSTD_LOGIC;
Sum, CarryOut : OUTSTD_LOGIC
);
END COMPONENT;
SIGNAL carry : std_logic_vector(7 DOWNTO 1);
BEGIN
f0: fulladder PORT MAP (
a => a(0),
b => b(0),
CarryIn => cin,
Sum => sum(0),
CarryOut => carry(1)
);
f1: fulladder PORT MAP (
a => a(1),
b => b(1),
CarryIn => carry(1),
Sum => sum(1),
CarryOut => carry(2)
);
f2: fulladder PORT MAP (
a => a(2),
b => b(2),
CarryIn => carry(2),
Sum => sum(2),
CarryOut => carry(3)
);
f3: fulladder PORT MAP (
a => a(3),
b => b(3),
CarryIn => carry(3),
Sum => sum(3),
CarryOut => carry(4)
);
f4: fulladder PORT MAP (
a => a(4),
b => b(4),
CarryIn => carry(4),
Sum => sum(4),
CarryOut => carry(5)
);
f5: fulladder PORT MAP (
a => a(5),
b => b(5),
CarryIn => carry(5),
Sum => sum(5),
CarryOut => carry(6)
);
f6: fulladder PORT MAP (
a => a(6),
b => b(6),
CarryIn => carry(6),
Sum => sum(6),
CarryOut => carry(7)
);
f7: fulladder PORT MAP (
a => a(7),
b => b(7),
CarryIn => carry(7),
Sum => sum(7),
CarryOut => cout
);
END ripple;