Exams/m2014 q4k_hdlbits

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);

    reg [3:1] q;
    
    always @ (posedge clk)
        begin
            if (~resetn)
            {q,out} <= 4'b0;
           else
               begin
                   //q[3] <= in;
                   //q[2] <= q[3];
                   //q[1] <= q[2];
                   //out <= q[1];   
                   {q,out} <= {in, q};
               end         
        end
 
endmodule