vhdl8三种方式实现38译码器

之前用连接符&做过38译码器，觉得有点复杂。这次换几个方法：
1.when_else语句
代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity decoder38_1 is
port( a: in std_logic_vector(2 downto 0);
  b: out std_logic_vector(7 downto 0));
end decoder38_1;
architecture Behavioral of decoder38_1 is
signal b1:std_logic_vector(7 downto 0);
begin
   b1<="11111110"when a="000"else
    "11111101"when a="001"else
    "11111011"when a="010"else
    "11110111"when a="011"else
    "11101111"when a="100"else
    "11011111"when a="101"else
    "10111111"when a="110"else
    "01111111"when a="111"else
    "11111111";
  b<=b1;
end Behavioral;

在写这次代码的时候有两次报错：
1.ERROR:HDLCompiler:1690 - “E:\vhdl\decoder38_1\decoder38_1.vhd” Line 33: This construct is only supported in VHDL 1076-2008
原因我在结构体中用了process（a），去掉就可以了。
2.when_else最后一行是要加上；的
3.有的时候，端口不便于赋值，可以使用signal。
仿真：
要注意：这里没有用时钟，要删除constant和关于时钟的操作

2.case语句：
case和when_else一定要注意区分，when_else不要加载process中，
case一定要加载process中，否则会报错！！！

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder38_2 is
port( a: in std_logic_vector(2 downto 0);
  b: out std_logic_vector(7 downto 0));
end decoder38_2;
architecture Behavioral of decoder38_2 is
begin
process(a)
begin
 case a is
  when "000"=> b <="11111110";
  when "001"=> b <="11111101";
  when "010"=> b <="11111011";
  when "011"=> b <="11110111";
  when "100"=> b <="11101111";
  when "101"=> b <="11011111";
  when "110"=> b <="10111111";
  when "111"=> b <="01111111";
  when others=> b <="11111111";
 end case;
end process;
end Behavioral;```
仿真：

–ujs-lili
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
– Uncomment the following library declaration if using
– arithmetic functions with Signed or Unsigned values
–USE ieee.numeric_std.ALL;
ENTITY decoder38_2_tb IS
END decoder38_2_tb;
ARCHITECTURE behavior OF decoder38_2_tb IS
– Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder38_2
PORT(
a : IN std_logic_vector(2 downto 0);
b : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
–Inputs
signal a : std_logic_vector(2 downto 0) := (others => ‘0’);
–Outputs
signal b : std_logic_vector(7 downto 0);
– No clocks detected in port list. Replace below with
– appropriate port name
BEGIN
– Instantiate the Unit Under Test (UUT)
uut: decoder38_2 PORT MAP (
a => a,
b => b
);
– Stimulus process
stim_proc: process
begin
a<=“000”;
wait for 100 ns;
a<=“001”;
wait for 100 ns;
a<=“010”;
wait for 100 ns;
a<=“011”;
wait for 100 ns;
a<=“100”;
wait for 100 ns;
a<=“101”;
wait for 100 ns;
a<=“110”;
wait for 100 ns;
a<=“111”;
wait for 100 ns;
end process;
END;
``

3.to_integer转换

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity decoder38_3 is
port( a: in std_logic_vector(2 downto 0);
  b: out std_logic_vector(7 downto 0));
end decoder38_3;
architecture Behavioral of decoder38_3 is
begin
 process(a)
 begin
  b<=(others=>'1');
  b(CONV_integer(a))<='0';--从std_logic变成integer
 end process;
end Behavioral;

注意：是conv不是to！
仿真：

4.学习
to_integer是dataio公司的，程序包ops一般不用，
to_vector也是…写上去之后会发现一直说未声明。
ERROR:HDLCompiler:69 - “E:\vhdl\decoder38_3\decoder38_3.vhd” Line 33: is not declared.