VHDL设计一个同步清零的JK触发器

1、设计一个同步清零的JK触发器，其引脚名称和逻辑功能如下表所示。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY jk IS
PORT (clk, clr, j,k : IN STD_LOGIC;
q, nq : buffer STD_LOGIC);

END jk;
ARCHITECTURE arjk OF jk IS
	BEGIN
		PROCESS(clk) is
		BEGIN
			IF (clk'EVENT AND clk='1') THEN
				IF(clr='0') THEN
					q<='0';
					nq<='1';
				ELSE
					IF((j='0') and(k='1')) THEN
						q<='0';
						nq<='1';
					ELSIF ((j='1') and(k='0')) THEN
						q<='1';
						nq<='0';
					ELSIF ((j='1') and(k='1')) THEN
						q<=NOT q;
						nq<=NOT q;
					END IF;

				END IF;
		 	END IF;

	   END PROCESS;
END arjk;