module clk18(CP,RST,Ch,Cm,Hc,Sh,Sl,W,ddo,pin_50, pin_51);
input pin_50, pin_51;
input CP,RST,Ch,Cm,Hc;
output wire [7:0] Sh,Sl;
output wire [3:0] W;
output wire [7:0] ddo;
reg [14:0]Q;
wire Sp;
reg [5:0] S;
reg [3:0] Ml;
reg [2:0] Mh;
reg [3:0] Hl;
reg [1:0] Hh;
wire [7:0] Hhdo,Hldo,Mhdo,Mldo;
reg [6:0] Hhd,Hld,Mhd,Mld;
always @(posedge CP )
begin
if (RST==0)
begin
Hh<=2'd0;
Hl<=4'd0;
Mh<=3'd0;
Ml<=4'd0;
S<=6'd0;
end
else
if (Q!=15'd32767) Q<=Q+15'd1;
else
begin
Q<=15'd0;
case({Ch,Cm})
2'b11: begin
if (S!=6'd59) S<=S+6'd1;
else begin S<=6'd0;
if(Ml!=4'd9) Ml<=Ml+4'd1;
else begin Ml<=4'd0;
if (Mh!=3'd5) Mh<=Mh+3'd1;
else begin Mh<=3'd0;
if (Hc==0)
if ({Hh,Hl}==6'h11) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
else
if ({Hh,Hl}==6'h23) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
end
2'b10: begin
if (S!=6'd59) S<=S+6'd1;
else S<=6'd0;
if(Ml!=4'd9) Ml<=Ml+4'd1;
else begin Ml<=4'd0;
if (Mh!=3'd5) Mh<=Mh+3'd1;
else begin Mh<=3'd0;
if (Hc==0)
if ({Hh,Hl}==6'h11) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
else
if ({Hh,Hl}==6'h23) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
2'b01: begin
if (Hc==0)
if ({Hh,Hl}==6'h11) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
else
if ({Hh,Hl}==6'h23) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
if (S!=6'd59) S<=S+6'd1;
else begin S<=6'd0;
if(Ml!=4'd9) Ml<=Ml+4'd1;
else begin Ml<=4'd0;
if (Mh!=3'd5) Mh<=Mh+3'd1;
else Mh<=3'd0;
end
end
end
2'b00: begin
if (S!=6'd59) S<=S+6'd1;
else S<=6'd0;
if(Ml!=4'd9) Ml<=Ml+4'd1;
else begin Ml<=4'd0;
if (Mh!=3'd5) Mh<=Mh+3'd1;
else Mh<=3'd0;
end
if (Hc==0)
if ({Hh,Hl}==6'h11) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
else
if ({Hh,Hl}==6'h23) {Hh,Hl}<=6'h0;
else if(Hl!=4'd9) Hl<=Hl+4'd1;
else begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
endcase
case (Hh)
2'd0:Hhd<=7'b0;
2'd1:Hhd<=7'b0000110;
2'd2:Hhd<=7'b1011011;
default:Hhd<=7'b0;
endcase
case (Hl)
4'd0:Hld<=7'b0111111;
4'd1:Hld<=7'b0000110;
4'd2:Hld<=7'b1011011;
4'd3:Hld<=7'b1001111;
4'd4:Hld<=7'b1100110;
4'd5:Hld<=7'b1101101;
4'd6:Hld<=7'b1111100;
4'd7:Hld<=7'b0000111;
4'd8:Hld<=7'b1111111;
4'd9:Hld<=7'b1101111;
default:Hld<=7'b0;
endcase
case (Mh)
4'd0:Mhd<=7'b0111111;
4'd1:Mhd<=7'b0000110;
4'd2:Mhd<=7'b1011011;
4'd3:Mhd<=7'b1001111;
4'd4:Mhd<=7'b1100110;
4'd5:Mhd<=7'b1101101;
default:Mhd<=7'b0;
endcase
case (Ml)
4'd0:Mld<=7'b0111111;
4'd1:Mld<=7'b0000110;
4'd2:Mld<=7'b1011011;
4'd3:Mld<=7'b1001111;
4'd4:Mld<=7'b1100110;
4'd5:Mld<=7'b1101101;
4'd6:Mld<=7'b1111100;
4'd7:Mld<=7'b0000111;
4'd8:Mld<=7'b1111111;
4'd9:Mld<=7'b1101111;
default:Mld<=7'b0;
endcase
end
end
assign Sh=8'b00000001<<({S[5],S[4],S[3]});
assign Sl=~(8'b00000001<<({S[2],S[1],S[0]}));
assign W=4'b0001<<({Q[9],Q[8]});
assign Sp=Q[14];
assign Hhdo={1'b0,Hhd}&{W[3],W[3],W[3],W[3],W[3],W[3],W[3],W[3]};
assign Hldo={Sp,Hld}&{W[2],W[2],W[2],W[2],W[2],W[2],W[2],W[2]};
assign Mhdo={1'b0,Mhd}&{W[1],W[1],W[1],W[1],W[1],W[1],W[1],W[1]};
assign Mldo={1'b0,Mld}&{W[0],W[0],W[0],W[0],W[0],W[0],W[0],W[0]};
assign ddo=Hhdo+Hldo+Mhdo+Mldo;
endmodule