1.串行乘法器（8位为例）
1.1 verilog 程序
module mutilpiler(
clk,mutil_a,mutil_b,result
);
input clk;//时钟信号
input [7:0] mutil_a,mutil_b;//输入
output [15:0] result;//乘法结果
reg [15:0] result=16'b0;
reg [15:0] S0=0;//计算存储单元
reg [3:0] count=0;//计数 移位八次结束 3'b100
reg [7:0] mutil_b1;
initial
begin
mutil_b1=mutil_b;
S0=mutil_a;
end
always @(posedge clk)
begin
if(count==4'b1000) //移位8次，当计数器到8时重置
begin
result=0;
S0=mutil_a;
count=4'b0;//归零
mutil_b1=mutil_b;
end
else
begin
if(mutil_b1[0]==1'b1)
begin
result=result+S0;
S0=S0<<1;
end
else
begin
S0=S0+0;
S0=S0<<1;
end
count=count+1;
mutil_b1=mutil_b1>>1;
end
end
endmodule
1.2 testbench
module sim_mutilpiler(
);
reg [7:0] mutil_a,mutil_b;
reg clk;
wire [15:0] result;
initial
begin
clk=0;
mutil_a=8'b10000001;
mutil_b=8'b11111111;
end
always #5 clk=~clk;
mutilpiler m1(clk,mutil_a,mutil_b,result);
endmodule
1.3仿真图
有个问题，一开始会空八个时钟周期再进行计算，没想到啥原因。
2.并行乘法器
2.1 verilog 程序
module mutil_parallel(
clk,mutil_a,mutil_b,result
);
input clk;
input [7:0] mutil_a,mutil_b;
output reg [15:0] result;
reg [15:0] S1,S2,S3,S4,S5,S6,S7,S8;
initial result=15'b0;
always@(posedge clk)
begin
//result=15'b0;
S1=mutil_b[0]?{8'b0,mutil_a}:16'b0;
S2=mutil_b[1]?{7'b0,mutil_a,1'b0}:16'b0;
S3=mutil_b[2]?{6'b0,mutil_a,2'b0}:16'b0;
S4=mutil_b[3]?{5'b0,mutil_a,3'b0}:16'b0;
S5=mutil_b[4]?{4'b0,mutil_a,4'b0}:16'b0;
S6=mutil_b[5]?{3'b0,mutil_a,5'b0}:16'b0;
S7=mutil_b[6]?{2'b0,mutil_a,6'b0}:16'b0;
S8=mutil_b[7]?{1'b0,mutil_a,7'b0}:16'b0;//非阻塞赋值
//result<=15'b0;
result<=S1+S2+S3+S4+S5+S6+S7+S8;
end
endmodule
(emmm,网上看了好多也没明白，最简单的就直接用 乘法符号)