FPGA仿真笔记

仿真的时候先分模块仿真，每个模块仿真完成后，再一个模块一个模块的增量仿真。
一.生成仿真数据。

1.matlab 实数转16进制，量化到16位，保存16进制txt文件

singnal = sin(0:0.01:0.01*65535);
signal_hex = signal./max(signal)*32767; signal_hex=floor(signal_hex); %15位量化,16位保留为符号位，取整
dat(find(signal_hex<0)) = dat(find(signal_hex<0)) + 65535 + 1; %负数取反加一转换为补码
fid = fopen("signal_hex.txt","w"); fprintf(fid,'%x\n',dat);fclose(fid); %保存为txt

	function [] = hex_txt_gen(file_name,din,radix,symbol)
	signal_hex = din;
	ind = signal_hex<0;
	din_len = length(din);
	flag_chg = 2^radix;
if(strcmp(symbol,"signed"))
	for i=1:din_len
		if(ind(i))
			signal_hex(i) = signal_hex(i) + flag_chg; %取补码
		end
	end
end

signal_hex = uint32(siganl_hex);

fid = fopen(file_name,'w'); fprint(fid,"%d\n",signal_hex);fclose(fid);

2.Verilog 读取16进制txt文件

reg [15:0]signal [0:65535];
reg [15:0]data_in;
initial $readmemh("D:/FPGA/DATA/signal_hex.txt",signal,0,65535);
integrt i;
initial begin
	i <= 0;
	data_in <= 'd0;
	forever @(posedge clk) begin
		if(!rst_n) begin
			data_in <= 'd0;
			i <= 0;
		end else if(data_vld) begin
			data_in <= signal[i]
			i <= i + 1;
		else begin
			data_in <= data_in;
			i <= i;
		end
	end
end

3.保存仿真结果

integer data_out_file;
initial  begin
	data_out_file = $fopen("data_out.txt","w");
	if(data_out_file==0) begin
		$display("Err:open fail!");
		$finish;
	end
end

always @(posedge clk) begin
	if(data_out_vld) $fwrite(data_out_file,"%d\n",$signed(data_out));
end

4.matlab 导入仿真结果进行分析

data_out = load("data_out.txt");

5.Modelsim 重新编译

compile.bat
do {xxx_simulate.do}