hdlbits_Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
	
    parameter WL=0,WR=1,AH_L=2,AH_R=3;
    reg [1:0] state,next;
    
    always @ (*)
        begin
            case(state)
                WL: if (~ground) next = AH_L;
                else if (bump_left) next = WR;
                else next = WL;
                WR:if (~ground) next = AH_R;
                else if (bump_right) next = WL;
                else next = WR;
                AH_L: next = (ground)?WL:AH_L;
                AH_R: next = (ground)?WR:AH_R;
            endcase
        end
    
    always @(posedge clk, posedge areset)
        begin
            if (areset)
                state <= WL;
            else
                state <= next;
        end
    
    assign walk_left = (state == WL);
    assign walk_right = (state == WR);
    assign aaah = (state == AH_R) | (state == AH_L);
endmodule