ZC702开发板简介

最近拿到了一块Xilinx的ZC702rev D开发板,准备上手好好玩玩。主芯片Zynq-7020里面集成ARMCortex-A9双核和Xilinx的Artix 7FPGA,可以尝试嵌入式软件和FPGA协同开发,可玩度非常高。

 

先上个图。



板子的基本参数:

  • Zynq-7000 XC7Z020-1CLG484C AP SoC (667MHz)

Note: Zynq-7010/20支持的工作频率为:-1=667MHz,-2=733MHz,-3=800MHz。

  • 1 GBDDR3 component memory (four 256 Mb x 8 devices) (533MHz)

Note: Zynq-7010/20支持的DRAM工作频率为:DDR3=1066MHz,DDR2=800MHz,LPDDR2=800MHz。

  • 128 MbQuad SPI flash memory

Note: 板载的是Micron的25Q128A11E

  • USB2.0 ULPI (UTMI+ low pin interface) transceiver

Note: SMSC的USB3320

  • SecureDigital (SD) connector
  • USB JTAG interface via Digilent module
  • Clock sources:
  • Fixed200 MHz LVDS oscillator (differential)
  • I2Cprogrammable LVDS oscillator (differential)
  • Fixed33.33 MHz LVCMOS oscillator (single-ended)
  • Ethernet PHY RGMII interface with RJ-45 connector

Note: 用的PHY是Marvel的88E1116R,RGMII接口。

  • USB-to-UART bridge

Note: 用的是SiliconLab的CP2103

  • HDMIcodec

Note: 用的HDMI PHY是ADI的的ADV7511

  • I2Cbus

I2C busmultiplexed to:

  1. Si570user clock
  2. ADV7511 HDMI codec
  3. M24C08EEPROM (1 kB)
  4. 1-To-16 TCA6416APWR port expander
  5. RTC-8564JE real time clock
  6. FMC1LPC connector
  7. FMC2LPC connector
  8. PMBUS data/clock
  • StatusLEDs:
  1. Ethernet status
  2. Powergood
  3. FPGAINIT
  4. FPGADONE
  • UserI/O:
  1. Eightuser LEDs
  2. Twoprogrammable logic (PL) user pushbuttons
  3. PLuser DIP switch (2-pole)
  4. Twoprocessing system (PS) pushbuttons shared with PS 2-pole DIP switch
  5. Two PSuser LEDs
  6. Dualrow Pmod GPIO header
  7. Singlerow Pmod GPIO header
  • AP SoCPS Reset Pushbuttons:
  1. SRST_BPS reset button
  2. POR_BPS reset button
  • TwoVITA 57.1 FMC LPC connectors
  • Poweron/off slide switch
  • Powermanagement with PMBus voltage and current monitoring via TI power controllers
  • Dual12-bit 1 MSPS XADC analog-to-digital front end
  • Configuration options:
  1. QuadSPI flash memory
  2. USBJTAG configuration port (Digilent module)
  3. Platform cable header JTAG configuration port
  4. 20-pinPL PJTAG header
  5. 20-pinPL JTAG header

 

信息来自于ZC702User Guide, UG850 v1.1

========

板子的入口:

http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm

板子文档和针对ISE14.2的设计文件:

http://www.xilinx.com/support/documentation/zc702_14-2.htm

 

Zynq芯片和开源资源的列表:

http://www.xilinx.com/products/zynq-7000/third-party-documentation.htm

 

另外Xilinx提供了一个很不错的Sobel滤波的参考设计:

http://wiki.xilinx.com/zynq-base-trd-14-2



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