HDLBits 系列（20）移位寄存器（逻辑移位、算术移位、循环移位）

目录

4 bit的右移寄存器设计

100 bit循环移位寄存器

算术移位寄存器

---

4 bit的右移寄存器设计

先给出一个4位右移寄存器的设计题：

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

• areset: Resets shift register to zero.
• load: Loads shift register with data[3:0] instead of shifting.
• ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
• q: The contents of the shift register.

If both the load and ena inputs are asserted (1), the load input has higher priority.

题目过于简单，直接给出我的设计：

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    
    always@(posedge clk or posedge areset) begin
        if(areset) q <= 0;
        else if(load) q <= data;
        else if(ena) begin
            q <= {1'b0, q[3:1]};    
        end
        
    end

endmodule

---

100 bit循环移位寄存器

Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.

• load: Loads shift register with data[99:0] instead of rotating.
• ena[1:0]: Chooses whether and which direction to rotate.
  • 2'b01 rotates right by one bit
  • 2'b10 rotates left by one bit
  • 2'b00 and 2'b11 do not rotate.
• q: The contents of the rotator.

Module Declaration

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q);

也很简单，直接给出我的设计：

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    
    always@(posedge clk) begin
        if(load) q <= data;
        else begin
            if(ena == 2'b01) q <= {q[0], q[99:1]};
            else if(ena == 2'b10) q <= {q[98:0], q[99]};
            else ;
        end
    end

endmodule

---

算术移位寄存器

 

Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.

An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.

There is no difference between logical and arithmetic left shifts.

• load: Loads shift register with data[63:0] instead of shifting.
• ena: Chooses whether to shift.
• amount: Chooses which direction and how much to shift.
  • 2'b00: shift left by 1 bit.
  • 2'b01: shift left by 8 bits.
  • 2'b10: shift right by 1 bit.
  • 2'b11: shift right by 8 bits.
• q: The contents of the shifter.

Module Declaration

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 

不用看题目，都知道要做什么：

提示：

A 5-bit number 11000 arithmetic right-shifted by 1 is 11100, while a logical right shift would produce 01100.

Similarly, a 5-bit number 01000 arithmetic right-shifted by 1 is 00100, and a logical right shift would produce the same result, because the original number was non-negative.

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always@(posedge clk) begin
        if(load) q <= data;
        else if(ena) begin
            if(amount == 2'b00) q <= {q[62:0],1'b0};
            else if(amount == 2'b01) q <= {q[55:0],{8{1'b0}}};
            else if(amount == 2'b10) q <= {q[63],q[63:1]};
            else if(amount == 2'b11) q <= {{8{q[63]}},q[63:8]};
        end
        else ;
    end

endmodule