简易交通灯控制器Verilog

设计一个简单的交通灯控制器，他有5个状态，每个状态都具有可独立编程确定的时间参数（parameter），假设时钟频率为50Hz（如果仿真时间太长可以做适当的比例修改）。

路口交通灯示意图

设计代码

`timescale 1ns / 1ps
module Test1530(clk,reset,red1,yellow1,green1,red2,yellow2,green2);
input clk;
input reset;
output red1,yellow1,green1;
reg red1,yellow1,green1;
output red2,yellow2,green2;
reg red2,yellow2,green2;
reg [11:0] count;
parameter Y1Y2=0,R1Y2=1,G1R2=2,Y1R2=3,R1G2=4;
parameter timeR1Y2=250，timeG1R2,2500,timeY1R2=250,timeR1G2=2250;
reg [2:0] state;
/
always @(posedge clk)
   if(reset)
      begin
         count<=0;
         state<=Y1Y2;
         red1<=0;yellow1<=1;green1<=0;
         red2<=0;yellow2<=1;green2<=0;
      end
   else      
      case(state)   
         Y1Y2:begin
                 state<=R1Y2;
                 count<=1;
              end
         R1Y2:begin
                 if(count= =timeR1Y2)
                    begin
                       state<=G1R2;
                       red1=0;yellow1<=0;green1<=1;
                       red2=1;yellow2<=0;green2<=0;
                       count<=1;
                    end
                 else
                    begin
                       state<=R1Y2;
                       red1=1;yellow1<=0;green1<=0;
                       red2=0;yellow2<=1;green2<=0;
                       count<=count+1;
                    end
              end
         G1R2:begin
                 if(count= =timeG1R2)
                    begin
                       state<=Y1R2;
                       red1=0;yellow1<=1;green1<=0;
                       red2=1;yellow2<=0;green2<=0;
                       count<=1;
                    end
                 else
                    begin
                       state<=G1R2;
                       red1=0;yellow1<=0;green1<=1;
                       red2=1;yellow2<=0;green2<=0;
                       count<=count+1;
                    end
              end
         Y1R2:begin
                 if(count= =timeY1R2)
                    begin
                       state<=R1G2;
                       red1=1;yellow1<=0;green1<=0;
                       red2=0;yellow2<=0;green2<=1;
                       count<=1;
                    end
                 else
                    begin 
                       state<=Y1R2;
                       red1=0;yellow1<=1;green1<=0;
                       red2=1;yellow2<=0;green2<=0;
                       count<=count+1;
                    end
              end
         R1G2:begin
                 if(count= =timeR1G2)
                    begin
                       state<=R1Y2;
                       red1=1;yellow1<=0;green1<=0;
                       red2=1;yellow2<=0;green2<=0;
                       count<=1;
                    end
                 else
                    begin
                       state<=R1G2;
                       red1=1;yellow1<=0;green1<=0;
                       red2=0;yellow2<=0;green2<=1;
                       count<=count+1;
                    end
              end
         default:state<=Y1Y2;
         endcase
endmodule

测试代码

`timescale 1ns / 1ps
module Test1620;
reg clk;
reg reset;
wire red1,yellow1,green1,red2,yellow2,green2;
always begin
   #10 clk=1;
   #10 clk=0;
end 

initial begin
   clk=0;
   reset=1;
   #10000;
   reset=0;
end

Test1530 x1(.clk(clk),
            .reset(reset),
            .red1(red1),
            .yellow1(yellow1),
            .green1(green1),
            .red2(red2),
            .yellow2(yellow2),
            .green2(green2));
endmodule

仿真波形