HDLbits---Circuits---Sequential Logic---Shift Registers
1.Shift4moduletop_module(inputclk,inputareset,//asyncactive-highresettozeroinputload,inputena,input[3:0]data,outputreg[3:0]q);always@(posedgeclkorposedgeareset)beginif(areset)q<=0;elseif(load)q<=data;