HDLBits 系列（29）PS/2 mouse protocol（PS/2 packet parser and datapath）

目录

序言

原题传送

题目解释

我的设计

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序言

上篇博客：

HDLBits 系列（28）PS/2 mouse protocol（PS/2 packet parser）

只对PS/2 mouse protocol的数据流检测到了之后输出检测到了的标志done，但是没有输出检测数据，这一篇博客接着设计。

原题传送

Fsm ps2data

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

题目解释

有几个重点是：

done有效的时候要输出接受数据，这就意味着在状态DONE时刻，不能在改变输出数据了，然而，在DONE状态下有可能输入的数据是第一个字节，所以怎么办呢？

我的设计

那就将输入数据和状态延迟一拍吧，在D2状态里面处理，我的设计如下：

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    reg [1:0] state, next_state;
    localparam D1 = 0, D2 = 1, D3 = 2, DONE = 3;
 
    // State transition logic (combinational)
    always@(*) begin
        case(state)
            D1: begin
                if(in[3] == 1) next_state = D2;
                else next_state = D1;
            end
            D2: begin
                next_state = D3;
            end
            D3: begin
                next_state = DONE;
            end
            DONE: begin
                if(in[3] == 1) next_state = D2;
                else next_state = D1;
            end
            default: begin
                next_state = D1;
            end
        endcase
    end
    
    always@(posedge clk) begin
        if(reset) state <= D1;
        else state <= next_state;
    end

    // New: Datapath to store incoming bytes.
    reg [7:0] in_r;
    reg [1:0] state_r;
    always@(posedge clk) begin
        if(reset) begin 
            in_r <= 0;
            state_r <= D1;
        end
        else begin
            state_r <= state; 
            in_r <= in;
        end
    end
    
    reg [23:0] out_bytes_mid;
    always@(*) begin
        case(state)
            D1: begin
                if(in[3] == 1) out_bytes_mid[23:16] = in;
            end
            D2: begin
                if(state_r == DONE && in_r[3] == 1) begin
                    out_bytes_mid[15:8] = in;
                    out_bytes_mid[23:16] = in_r;
                end
                else out_bytes_mid[15:8] = in;
            end
            D3: begin
                out_bytes_mid[7:0] = in;
            end
            DONE: begin
                ;
            end
            default: begin
                ;
            end
        endcase
    end
    assign out_bytes = (done == 1)? out_bytes_mid:'bx;
    assign done = (state == DONE)?1:0;

endmodule

测试成功。