HDLbits---Circuits---Sequential Logic---Finite State Machines第一部分
1.Fsm1moduletop_module(inputclk,inputareset,//AsynchronousresettostateBinputin,outputout);//parameterA=0,B=1;regstate,next_state;always@(posedgeclkorposedgeareset)beginif(areset)state<=B;elsestate<=ne